The current trend is to integrate vertically by stacking packages (3D Packaging). There are several packaging formats currently being used to accomplish this: (1) Traditional Package-on-Package (PoP) with bare die or pin gate molding; (2) Package-in-Package (PiP); and (3) Thru-Mold Via (TMV).
In each of these formats, the space needed to accommodate the vertical structures limits the space available on the bottom package for the main logic die. The challenge is to maximize the die size allowed in the bottom package while maintaining the same package-to-package I/O currently used.
Until now, the main focus has been to reduce the BGA pitch of the top package so that more I/O can fit on one or two perimeter rows which then gives more space in the middle for the die in the bottom package. One challenge to this approach is with tighter pitches on the top package, the top package BGA ball becomes smaller which affects both stand-off, and collapse.
In TMV format, there is the added challenge of “building up” the solder within the TMV package to achieve a relatively tall bump with a tight pitch.
In the following description, the same or similar elements are labeled with the same or similar reference numbers.